Electrical Engineering Technical Interview Questions

Twelve electrical engineering interview questions, from RC circuits and op-amps to power factor and debugging, with what each tests and a model answer.

Many electrical engineering technical interview questions are built on fundamentals such as circuit theory, asked out loud with someone watching: find a Thevenin equivalent, sketch a capacitor charging, work out an op-amp's gain, explain power factor. What separates candidates is not knowing more topics but explaining the basics cleanly and then handling the follow-up ("what happens if the load changes?"). Below are twelve such questions, each with what it tests and a short model answer, then how to weight them by role and a one-week plan.

Before you prepare: find out the format

Formats vary between employers, so ask the recruiter before you study: who runs the technical round (a manager talking concepts, or engineers handing you a marker), whether there is a written test, and whether you present a past project. Whatever the format, be ready to explain every project on your resume at the level of "why this part and not another."

Circuit fundamentals

1. Find the Thevenin equivalent of this circuit

What it tests: methodical simplification instead of grinding through every node.

Model answer: remove the load. The Thevenin voltage is the open-circuit voltage across the two terminals. For the Thevenin resistance, short every independent voltage source, open every independent current source, and find the resistance looking back into the terminals. The payoff is that you can now swap loads and recompute in one line. Say out loud that the method assumes a linear circuit; it does not hold for nonlinear parts.

2. Sketch the capacitor voltage at t = 0 and afterwards (worked example)

What it tests: transient intuition, with numbers attached.

Suppose the interviewer draws a 5 V step feeding a 1 kΩ resistor in series with an uncharged 1 µF capacitor.

• At t = 0: the uncharged capacitor behaves like a short circuit. Its voltage is 0 V and the current is limited only by the resistor: 5 V / 1 kΩ = 5 mA.
• Time constant: τ = RC = 1 kΩ × 1 µF = 1 ms.
• After one time constant: the capacitor reaches 63.2% of the final voltage, about 3.16 V, and the current has fallen to 36.8% of its starting value.
• After five time constants (5 ms): 99.3% of the final voltage, which is treated as fully charged. The current is close to zero, so the capacitor now looks like an open circuit.

A weak answer draws the right curve with no numbers. A strong one labels 3.16 V at 1 ms and about 5 V by 5 ms, and states both limiting cases (short at the start, open at steady state) before being asked.

3. What is the gain of an inverting op-amp, and why?

What it tests: applying the ideal-op-amp rules, not reciting a formula.

Model answer: gain is −Rf/Rin. With Rf = 100 kΩ and Rin = 10 kΩ, that is −10. With negative feedback, the inverting input sits at the same voltage as the grounded non-inverting input (a virtual ground), and no current flows into either input. So all the current through Rin flows through Rf, which gives the ratio. Add that real op-amps only approximate those rules.

Power

4. What is power factor, and how would you correct a poor one?

What it tests: whether you understand real versus apparent power.

Model answer: power factor is real power divided by apparent power (watts over volt-amperes), which equals the cosine of the phase angle between voltage and current. A low power factor means the supply carries more current for the same useful power, so losses go up. For a lagging (inductive) load, add capacitance in parallel to supply some of the reactive power locally. In one worked example from an online tutorial, raising the power factor from 0.5 to 0.95 cuts the supply current from 5 A to 2.63 A while the real power stays the same.

5. Where does a transformer lose energy?

What it tests: practical component knowledge.

Model answer: two places. Copper losses are I²R heating in the windings and are usually the largest. Core (iron) losses come from hysteresis, the energy spent reversing the core's magnetisation every cycle, and eddy currents circulating in the core. Special steel alloys reduce hysteresis loss; building the core from thin laminations reduces eddy currents.

6. How do line and phase voltages relate in wye and delta connections?

What it tests: three-phase fluency.

Model answer: in a wye (star) connection, line voltage is √3 times phase voltage and line current equals phase current. In a delta connection, line voltage equals phase voltage and phase current is line current divided by √3. Quick check: 35 V line-to-line in wye is about 20 V per phase.

Electronics and board design

7. Drive a relay coil from a microcontroller pin. What do you need?

What it tests: whether you have built circuits, not just analysed them.

Model answer: a microcontroller pin usually cannot supply the coil current, so use a MOSFET as a low-side switch. A MOSFET is voltage-controlled and draws essentially no gate current, which suits a logic output. Some MOSFETs need 3 V to 4 V or more on the gate before they switch on, so pick a logic-level part. Low RDS(on) keeps the I²R heat in the MOSFET down. Then the detail that shows hands-on experience: a flyback diode across the coil, because the inductor's back-EMF at turn-off will otherwise hit the MOSFET.

8. Why do decoupling capacitors go right next to the IC?

What it tests: layout awareness.

Model answer: a small capacitor, typically 0.01 µF to 0.1 µF, placed as close to the power pin as possible acts as a high-frequency filter and gives the IC a stable supply with little noise. Put it far away and it does less, and it may even radiate the IC's switching noise. A larger capacitor, in the 10 µF to 100 µF range per board, handles lower-frequency filtering.

Signals and control

9. What happens if you sample a signal too slowly?

What it tests: the sampling theorem in practice.

Model answer: the sampling rate must exceed twice the highest frequency in the signal. Content above half the sampling rate does not disappear; it shows up at a lower frequency that was never in the original signal (aliasing). So you place an analog low-pass anti-aliasing filter before the ADC, chosen for the sample rate you plan to use.

10. What is phase margin, and what happens when it is too small?

What it tests: reasoning about feedback stability.

Model answer: phase margin is how far the loop's phase is from −180° at the frequency where loop gain falls to unity (0 dB). It is the extra phase lag the loop can absorb before it oscillates. Zero or negative margin with gain above unity means instability; low positive margin shows up as ringing. Op-amps are commonly compensated for at least about 45°, and designers often aim for around 60°. Mention unprompted that capacitive loads reduce it.

Debugging and judgement

11. A board works on the bench but fails intermittently in the field. How do you find the cause?

What it tests: method under ambiguity. The interviewer is listening for order, not one right answer.

Model answer: collect the conditions of each failure (temperature, load, time since power-up) and recreate them on the bench. Then work from the cheapest checks to the most expensive: supply rails under load (with a scope, not a multimeter, to catch dips), connectors and solder joints, thermal behaviour, then signal integrity. Change one thing at a time and write down what each test ruled out. Close with how you would stop it recurring.

12. Tell me about a design trade-off you made

What it tests: judgement and communication, where behavioral and technical questions meet.

Model answer: use STAR (Situation, Task, Action, Result), and spend most of your time on the Action: what you personally weighed and decided. Name the competing constraints (say, cost against thermal margin), the options, why you chose one and how you verified it. End with a measurable result and what you would do differently. Use a real project; the follow-ups will test it.

How to weight these by role

• Entry-level: expect questions 1 to 3, 9 and 12 most, and treat your capstone or internship project as the main exhibit. A PE license is not required for entry-level jobs, but if you have passed the Fundamentals of Engineering (FE) exam, generally a step toward a state PE license, say so.
• Design engineer (board or circuit): go deep on 3, 7, 8 and 11, and be ready to defend every component choice.
• Power engineer: 4 to 6 are the core; review protection and fault analysis too. Our power system interview questions cover that side in more depth.
• Embedded or firmware-adjacent: add 7, 9 and 11, then real-time topics; see the RTOS interview questions.

A one-week preparation plan

• Days 1–2: re-solve one problem of each type above by hand, timed, saying each step out loud.
• Day 3: write a two-sentence "why this part, why this approach" for every project on your resume.
• Day 4: prepare three STAR stories: a trade-off, a failure you debugged, and a disagreement on a team.
• Day 5: do a mock round with a friend who draws you an unfamiliar circuit; solving someone else's sketch is the skill being tested.
• Days 6–7: fill gaps for your role and re-read the job posting for tools or standards it names.

If you want support during the interview itself, Verve AI's Interview Copilot listens to the conversation and shows suggestions only you can see. Upload your resume and the job details and add your STAR stories to its Knowledge Base, so the suggestions draw on your own projects. More role guides are in the interview questions library.

Sources

• Thevenin method (short voltage sources, open current sources; Vth as open-circuit voltage; limits for nonlinear circuits): https://www.electronics-tutorials.ws/dccircuits/dcp_7.html
• RC time constant, 63.2% at 1τ, 99.3% at 5τ, capacitor as short at t = 0: https://www.electronics-tutorials.ws/rc/rc_1.html
• Inverting op-amp gain −Rf/Rin, 100 kΩ / 10 kΩ example, virtual ground, ideal rules: https://www.electronics-tutorials.ws/opamp/opamp_2.html
• Power factor definition, losses and current at low PF, correction from 0.5 to 0.95 cutting current from 5 A to 2.63 A: https://www.electronics-tutorials.ws/accircuits/power-factor.html
• Transformer copper and core losses, hysteresis, laminations: https://www.electronics-tutorials.ws/transformer/transformer-basics.html
• Wye and delta line/phase relationships, 35 V line to about 20 V phase example: https://www.electronics-tutorials.ws/transformer/three-phase-transformer.html
• MOSFET as a voltage-controlled device with no gate current: https://www.electronics-tutorials.ws/transistor/tran_6.html
• MOSFET switch gate threshold (3 V to 4 V), RDS(on) heating, flyback diode: https://www.electronics-tutorials.ws/transistor/tran_7.html
• Decoupling capacitor values, placement near the power pin, 10 µF to 100 µF per board: https://toshiba.semicon-storage.com/us/semiconductor/knowledge/faq/logic_common/logic_common_06.html
• Sampling rate above twice the highest frequency, aliasing, anti-aliasing filters: https://en.wikipedia.org/wiki/Aliasing
• Phase margin definition, ringing, 45° minimum and 60° typical targets: https://en.wikipedia.org/wiki/Phase_margin
• STAR structure and emphasis on your own actions and quantified results: https://capd.mit.edu/resources/the-star-method-for-behavioral-interviews/
• PE license not required for entry-level jobs; FE exam as a step toward the PE: https://www.bls.gov/ooh/architecture-and-engineering/electrical-and-electronics-engineers.htm